Semiconductor devices such as memory devices may include one or more output pins and one or more output buffers to transmitting data to other devices in the system. To improve the transmission of data, the impedance of the transmitting device may be matched to the impedance of the transmission network and receiving device. Impedance matching may allow for higher frequency of data transmission and reduce distortion caused in part by reflections occurring at an interface having an impedance mismatch.
To reduce the effects of impedance mismatches, manufacturing control of the output drivers may be employed to select a precise impedance value to match a transmission network and receiving device. However, manufacturing control can achieve only limited accuracy in matching the impedance value of an output buffer. Accordingly, semiconductor devices may employ a calibration circuit to adjust the impedance of one or more output buffers after the buffers are physically fabricated.
Examples of memory devices including calibration circuits are described in U.S. Published Application Number 2007/0263459 entitled “Method and apparatus for output driver calibration,” which publication is hereby incorporated by reference in its entirety. An example of a memory device 10 including an output driver calibration circuit 30 is shown in FIG. 1. The memory device 10 includes a plurality of physical connection terminals 12 for electrically connecting the memory device 10 to other devices within a memory or other system. Various ones of the pins 12 may couple to one or more busses, such as the address bus 14, data bus 16, control bus 18, or combinations thereof. During operation, a memory controller 13 may communicate with the memory device 10. Generally, the memory device 10 includes an array 20 of memory cells coupled to a row decoder 22 and column decoder 24. Responsive to address signals received from the memory controller 13, the row and column decoders 22, 24 may select the appropriate row and column of the memory array 20 for reading or writing as indicated by a command received from the memory controller 13. Data may then be written to or read from the selected memory cell. Data read from the selected memory cell is coupled to the data bus 16 through an output circuit 26 that includes a plurality of output drivers 28.
A calibration circuit 30 adjusts the impedance of one or more of the output drivers 28. The calibration circuit 30 is coupled to a calibration terminal 32 coupled to an external calibration resistor 34. The calibration resistor 34 may be selected responsive to a calibration command received from the memory controller 13, the calibration circuit 30 adjusts the impedance of one or more output drivers 28 based on the voltage at the calibration terminal 32, which is in turn determined by the calibration resistor 34.
An example of an implementation of calibration circuit 30 is shown in FIG. 2. The calibration circuit 30 includes a pull-up driver 202 and a pull-down driver 204. The pull-up driver 202 includes a p-channel variable impedance circuit 62 coupled to the calibration resistor 34 at the calibration terminal 32. The voltage at the calibration terminal is coupled to pull-up calibration logic 54. Responsive to a calibration command, the pull-up driver 202 is turned on, and the pull-up calibration logic may compare the voltage at the calibration terminal 32 with a reference voltage, Vref, and adjust the p-channel variable impedance circuit 62 to achieve a desired voltage at the calibration terminal 32. For example, if a power supply voltage 206 is VCCQ and the calibration resistor 34 is coupled to ground, the pull-up calibration logic 54 may adjust the p-channel variable impedance circuit 62 such that the voltage at the calibration terminal 32 is ½ VCCQ. Once the p-channel variable impedance circuit 62 of the pull-up driver 202 has been calibrated, the pull-up driver 202 may be coupled to the pull-down driver 204 as shown. A second p-channel variable impedance circuit 82 is adjusted in a similar manner to the p-channel variable impedance circuit 62. The pull-down calibration logic 88 compares a voltage at a node 64 to the reference voltage Vref and adjusts an impedance of an n-channel variable impedance circuit 84. In this manner, the voltage at the node 64 may also be adjusted to equal ½ VCCQ.
Based on the adjustments necessary to the p-channel variable impedance circuit 62 and the n-channel variable impedance circuit 84, the pull-up and pull-down calibration logic couple respective control signals 106 and 108 to the output circuit for use in configuring the output impedance of the output buffers.
Accordingly, by coupling a known calibration resistor 34 to the memory device 10, the impedance of output drivers may be adjusted to improve matching with a transmission network, other device coupled to the memory devices, or combinations thereof.